Semiconductor memory device

ABSTRACT

A semiconductor memory device operable at a high speed and having a high density of integration is disclosed. The memory device comprises a memory cell array consisting essentially of insulated-gate field effect transistors and peripheral circuits including bipolar transistors with their emitters coupled in common in an ECL configuration.

The present invention relates to a semiconductor memory device.

Semiconductor memory devices currently in use can in general be classified into two groups depending on the fields of application--one featuring high speed operation and the other featuring a large memory capacity. Attaining a high speed operation has inevitably resulted in large amount of power consumption, because a large power is required in memory cell arrays and peripheral circuits. In consequence, it has been difficult to obtain a large memory capacity on a semiconductor chip because of the limitations on total power consumption. Attaining a large memory capacity has sacrificed operating speed. Therefore, a semiconductor memory device operable at a high speed and having a large capacity has been hard attain.

In view of device structures and manufacturing processes, bipolar transistors have been used in high speed semiconductor memories. Because of their low impedance characteristic, bipolar transistors can operate at a very high speed. However, they consume large amounts of power, and their production yield has not been high because the manufacturing process to produce them has been complicated and lengthy. Insulated-gate field effect transistors (hereinafter referred to as IGFET) have been used in semiconductor memories featuring a large memory capacity. The manufacturing process for IGFETs is only about half as complicated and lengthy of that of bipolar transistors and has a good production yield, proving to be suitable for large capacity devices. However, the conduction resistances of IGFETs are large, and the devices are not suitable for high speed operation.

Recently, a RAM with MOS transistor construction having a high speed by virtue of bipolar transistors incorporated in part of its peripheral circuits was proposed in the 1978 IEEE International Solidstate Circuits Conference Digest of Technical Papers, Pages 110-111. The RAM uses bipolar transistors, which perform an emitter follower function, as loads for the output section of the peripheral circuits constructed with MOS transistors. Peripheral circuits of those RAMs attained a high speed to some extent. However, they did not have sufficiently high speed for the following reasons.

The peripheral circuits used inverter circuits of so-called CMOS construction as input circuits, and only input logic values at the TTL level (generally, 2-0.8 V), which have a large amplitude, could be used. For this reason, the foregoing emitter follower transistors could be operated only at the relatively slow speed of TTL circuits. As is well known, a severe limitation is placed on temperature and voltage variation coefficients for the interface level to ECLs which are known to be the fastest bipolar logic circuits. However, as the threshold voltage of a MOS transistor varies at about ±0.2 V even in the same chip in the said CMOS inverter circuit, signals of an ECL level cannot be handled simply.

It is an object of the present invention to provide a high-speed and large capacity semiconductor memory device.

It is another object of the present invention to provide a memory device operable with small power consumption.

A memory device according to the present invention comprises a memory cell array including a plurality of memory cells consisting essentially of IGFETs and peripheral circuits including emitter coupled bipolar transistors constituting emitter coupled logic circuits.

The present invention permits the realization of low power consumption and high integration by making memory cells with IGFETs. According to the present invention, peripheral circuits such as selection circuits for selecting the memory cells in the memory cell array, read and write control circuits, sense amplifier circuits, and other function circuits, which substantially employ bipolar transistors, can operate at high-speeds. IGFETs may be mixed in making the peripheral circuits depending on the necessity. Thus, the advantages of IGFETs and bipolar transistors are demonstrated to the maximum.

According to the present invention, IGFETs used in the memory cells can also reduce the power consumption, and be arranged in a smaller area on a semiconductor chip compared with bipolar transistors. Also, they are easy to produce. Bipolar transistors are used in the peripheral circuits to permit high speed operation. In the peripheral circuits, bipolar transistors are operated by applying inputs to the bases of the bipolar transistors, and outputs can be taken out either from the collectors or emitters of the transistors. As a result, there is an increase in the design freedom, and designing is thereby made easier.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing a known flip-flop type memory cell using P-Ch MIS transistors;

FIG. 2 is a circuit diagram showing a known flip-flop type memory cell using bipolar transistor;

FIG. 3 is a circuit diagram showing a semiconductor memory device according to a preferred embodiment of the present invention;

FIG. 4 is a circuit diagram showing an address buffer circuit in FIG. 3;

FIG. 5 shows a circuit diagram showing an example of an address decoder and driver circuit in FIG. 3;

FIG. 6 is a circuit diagram showing an example of the multiplexer circuit 16 in FIG. 3;

FIG. 7 is a circuit diagram showing an example of the read/write control circuit 14 in FIG. 3;

FIG. 8 is a circuit diagram showing an example of the differential amplifier 17 in FIG. 3;

FIG. 9 is a circuit diagram showing an example of the output sense amplifier circuit 15 in FIG. 3; and

FIG. 10 shows a circuit diagram of an example of the reference voltage generator circuit 19 in FIG. 3:

The present invention will be explained in detail by referring to the drawings.

A memory cell employing IGFETs shown in FIG. 1 and a memory cell employing bipolar transistors shown in FIG. 2 have been widely known. In FIG. 1, gates and drains of P-channel IGFETs Q₁ and Q₂ are cross-coupled, while their sources are grounded. The drains of IGFETs and Q₁ and Q₂ are coupled to the negative power source V_(EE) through depletion type load P-channel IGFETs Q₃ and Q₄ and to digit lines D_(i) and D_(i) through P-channel IGFETs Q₅ and Q₆. The gates of the transistors Q₃ and Q₆ are connected to a word line W_(j).

Because the basic characteristic of an IGFET resides in a voltage amplification operation, IGFETs Q₃ and Q₄ can be small only to compensate for the leak current of the transistors Q₁ and Q₂. The read current flowing into the digit line D_(i) or D_(i) from the memory cell is caused by the conduction resistance of IGFETs Q₁ and Q₅, or Q₂ and Q₆ and is not greatly affected by the scale of the memory capacity or power consumption.

In FIG. 2, the memory cell comprising multi-emitter transistors T₁ and T₂ having cross-coupled bases and collectors, and emitters which connect to the world line W_(Bj). The collectors are connected to the word line W_(Tj) through load resistors R₁ and R₂. Other emitters of the transistors T₁ and T₂ are connected to the digit lines D_(i) and D_(i) respectively. It is necessary to supply a base current of I_(D) /(1+h_(FE)) to cause a read current I_(D) to flow digit line D_(i) when the transistor T₁ is conducting. "h_(FE) " is a current amplification factor of the bipolar transistor. The current is regulated by the load resistors R₁ of the flip-flop, and the voltage drop R₁ I_(D) /(1+h_(FE)) of the load resistor is limited by the forward voltage V_(D) of Schottky barrier diodes SD₁, SD₂ which are arranged in parallel with the load resistors R₁ and R₂. Therefore, the amount of base current is limited by this limitation level. The holding current I_(H) of the memory cells and load resistor R₁ have a relationship expressed by RI_(H) ≈300 mV, and the following relationship is established between the holding current I_(H) and the read current I_(D) :

    I.sub.D /(1+h.sub.FE)≈I.sub.D /h.sub.FE <I.sub.H ˜2I.sub.H (1)

The holding current I_(H) becomes smaller the larger the bit capacity. Its typical level is about 50 μA and 10 μA for 1024 bit and 4096 bit memories, respectively. Consequently, assuming the current amplification factor h_(FE) to be 20 which is allowed in terms of practical manufacturing process, the read current will be (50 μA˜100 μA)×20=1 mA˜2 mA for the 1024 bit memory, while the read current I_(D) will be 200 μA˜400 μA for the 4096 bit memory. Applying a similar calculation for 16 kbit memory I_(D) ≃60 μA˜120 μA with I_(H) ≃3 μA will be obtained. Therefore, the memory cell employing bipolar transistors shown in FIG. 2 will have a smaller read current the larger the bit capacity, proving that it is not suitable for a large capacity. Therefore, it will be advantageous to form the memory cell array sharing a large area on a semiconductor chip with IGFETs which have a shorter manufacturing process compared with that for bipolar transistors.

With reference to FIG. 3, a semiconductor memory device according to the present invention will be described in detail. The memory cell array 11 has memory cells made of IGFETs as shown in FIG. 1. This memory cell array 11 has a matrix structure of j rows by i columns (i×j bits). In connection with FIG. 1, wherein P-channel IGFETs are employed, N-channel IGFETs or complementary type IGFETs (so-called CMOS's) can be employed in place of the P-channel IGFETs. An X-address buffer circuit 12_(x) receives X address inputs X_(o) ˜X_(m). A Y-address buffer circuit 12_(y) receives Y address inputs Y_(o) ˜Y_(n). The address buffer circuit 12_(x) and 12_(y) consist of both IGFETs and bipolar transistors, and their representative circuits are shown in FIG. 4. The outputs of the address buffer circuits 12_(x) and 12_(y) are respectively supplied to address driver circuits 13_(x) and 13_(y). Outputs of the driver circuit 13_(x) drive the word lines of the memory cell array 11 and outputs of the driver circuit 13_(y) control a multiplexer 16. A representative example of these address driver circuits 13_(x) or 13_(y) is shown in FIG. 5 per one bit. There are arranged 2^(m) =j pieces of the circuits shown in FIG. 5 in the driver circuit 13_(x), and 2^(n) =i pieces of the circuits in the driver circuit 13_(y) to select one of the memory cells. Read/write control circuit 14 (in FIG. 3) receives a chip select signal C_(s), write enable signal W_(E), and data D_(IN) from outside and sends a control signal W_(c) /W_(c) to the multiplexer circuit 16, and signal W_(E) complementary in phase to the write enable signal W_(E) to an output amplifier circuit 15, respectively. This circuit 14 is shown in FIG. 7.

The multiplexer circuit 16 receives the output of the address driver circuit 13_(y) and the control signal W_(c) /W_(c) of the read and write control circuit 14 and receives read data or sends write data to a digit line pair to be selected among i pairs of digit lines. The multiplexer circuit 16 for instance, can be constructed as shown in FIG. 6. A differential sense amplifier 17 is provided for each digit line pair of the memory cell array 11, by which read out data of one digit line pair selected is amplified. As an example, these differential amplifiers 17 can be structured as shown in FIG. 8. The read out data amplified by the differential amplifiers 17 are converted into output levels ultimately desired in the output amplifier circuit 15 and are sent to the output terminal 18. The circuit 15 can be, for instance, constructed as shown in FIG. 9.

The reference voltages to operate the circuits 12_(x), 12_(y), 13_(x), 13_(y), and 14 through 17 of these peripheral circuits are generated by a reference voltage generator circuit 19, which can be constructed, for instance, as shown in FIG. 10.

Below, each circuit referred to above will be explained in more detail. For the sake of making the explanation easier, an emitter coupled logic (referred to as ECL in the following) level will be assumed for interface. For this reason, the highest potential of the power supply is 0 V, and the lowest potential is -5.2 V, which is designated V_(EE). The input and output levels are -0.8 and -1.8 V for the high and low levels, respectively. The present invention, however, can be applied to processing on the so-called TTL level.

Referring to FIG. 10, the reference voltage generator circuit 19 will be explained first. A reference voltage V_(CCB) used for a regulated current source and reference voltages V_(R0), V_(R1), and V_(R2) needed for the ECL circuits are generated by this circuit 19. The collector of the bipolar transistor T₅ is grounded, and its emitter is connected to one end of a depletion type IGFET Q₇ through serially connected diodes D₁ and D₂. The other end and gate of IGFET Q₇ are connected to the low potential V_(EE). Voltages V_(R0), V_(R1), and V_(R2) are obtained from the emitter of the transistor T₅, from the junction point of the diodes D₁ and D₂, and from the junction point of the diode D₂ and IGFET Q₇, respectively. One end of a depletion type IGFET Q₈ is grounded, while the other end is connected to the low potential V_(EE) through a depletion type IGFET Q₉ -diodes D₃ -D₄ and depletion type IGFET Q₁₀. The gates of IGFETs Q₈, Q₉, and Q₁₀, are connected to the low potential V_(EE). The junction point of IGFETs Q₈ and Q₉ is connected to the base of the transistor T₅. The junction point of the transistor Q₉ and diode D₃ is connected to the base of the bipolar transistor T₆ to derive the voltage V_(CCB) from the emitter of the transistor T₆, which is connected to the low potential through a depletion type IGFET Q₁₁. In this connection, the transistor T₇ in the circuit shown in FIG. 4, for example, may be deleted so that the reference voltage V_(CCB) may be omitted from the generator circuit of FIG. 10.

The reference voltage V_(R0) is a used as a reference voltage for the ECL level, and generally takes a value of -1290 mV. And hence if a forward voltage of the diodes D₁ and D₂ is assumed to be 800 mV, the reference voltages V_(R1) and V_(R2) becomes V_(R1) =-1290 mV-800 mV=-2090 mV and V_(R2) =-2090 mV-800 mV=-2890 mV. IGFETs Q₇ through Q₁₁ used in this circuit 19 having hatched gate sections are depletion type IGFETs and may be considered merely as resistors. Those without hatching in the gate sections are enhancement type IGFETs. By appropriately designing each conduction resistance value of IGFETs Q₈, Q₉, and Q₁₀, in well known manner, voltages of -1290 mV+800 mV=-490 mV and about 400 mV can be generated at the base of the transistor T₅ and between the source and drain of IGFET Q₁₀, respectively. As a result, the reference voltage V_(CCB) takes a value that is higher than the voltage V_(EE) by the value of 400 mV+800 mV=1200 mV assuming the forward voltages of the diodes D₃ and D₄ and a base-emitter voltage of the transistor T₆ to be 800 mV.

FIG. 4 shows the circuit 12 corresponding to one of the address buffer circuits 12_(x) and 12_(y). The bipolar transistors T₈ and T₉ form ECL 20. ECL 20 differs from ordinary ECLs in that gates and drains of the P-channel IGFETs Q₁₃ and Q₁₄ are cross-coupled as load elements of the transistors T₈ and T₉. By selecting the threshold voltages of IGFETs Q₁₃ and Q₁₄ at about +0.2˜+0.5 V, the transistor T₈ conducts when the address input A_(I) (either one of X_(o) ˜X_(m), or Y_(o) ˜Y_(n)) applied to the base of the transistor T₈ through an emitter follower transistor T₁₀ is at a high level, to cause a current to flow from the transistor Q₁₃. For this reason, the drain potential of IGFET Q₁₃ lowers from 0 V to a specific potential. The gate potential of IGFET Q₁₄ also lowers at the same time, and conduction resistance of this transistor Q₁₄ becomes small, to accelerate the rise in the collector potential of the transistor T₉. The gate potential of IGFET Q₁₃ rises to 0 V at this time so that the conduction resistance of IGFET Q₁₃ increases. Therefore, the power consumption is reduced. Outputs a_(I) and a_(I) are led out from the collectors of the transistors T₉ and T₈. The amplitude levels required for them depend on the respective circuitry designs. In this case, -1 to -2 V is generally considered sufficient. Therefore, by appropriately setting the conduction resistances of IGFET Q₁₂, Q₁₃ and Q₁₄ to obtain gate voltages of -1 to -2 V, the required amplitudes can be obtained easily. As address input A_(I), the X side has X_(o) ˜X_(m), and the Y side, Y_(o) ˜Y_(n), and outputs X_(m), X_(m) (m=o˜m) and Y_(n), Y_(n) (n=o˜n) in in-phase and antiphase are generated as a_(I) and a_(I). The IGFET Q₁₅ operates as load element of the emitter follower transistor T₁₀.

The address driver circuits 13_(x) and 13_(y) shown in FIG. 5 have the same structure. Therefore, the circuit 13 and one of its outputs will be explained by referring to FIG. 5. The outputs X_(o) ˜X_(m) of the address buffer circuit 12 are selectively supplied to bases of the transistors Td_(o) ˜Td_(m) which perform as an emitter follower type OR gate. These transistors Td_(o) ˜Td_(m) perform a decoder operation. Consequently, 2^(m) =j circuits corresponding to that of FIG. 5 are provided in the address driver circuit 13_(x). Receiving various combinations of address signals x_(m), x_(m) (m=0˜m), a voltage that will become a selective level will be generated for only one word line out of j word lines, generating voltages that will become non-selective levels for all the other word lines. In other words, voltages are generated so that only one output will have -1 to -2 volt among j outputs d_(I) while all the other wires will have 0 V. The decode outputs from the commonly coupled emitters of the transistors Td_(o) ˜Td_(m) are supplied to the base of one bipolar transistor T11 in ECL circuit 21, which has the same configuration as that for the ECL circuit 20 shown in FIG. 4, while output d_(I) is led from the collector of the other bipolar transistor T₁₂.

In the read and write control circuit 14, the chip select signal C_(S) and write enable signal W_(E) are supplied to the bases of the bipolar transistors T₁₃ and T₁₄ as shown in FIG. 7. The collectors of the transistors T₁₃ and T₁₄ are grounded, and their emitters are connected to the low potential V_(EE) through the diodes D₅ and D₆ and IGFETs Q₁₆ and Q₁₇. The junction points of the diode D₅ and IGFET Q₁₆ and the diode D₆ and IGFET Q₁₇ are coupled to the bases of the bipolar transistors T₁₅ and T₁₆, respectively. The input data signal D_(IN) is supplied to the base of the bipolar transistor T₁₈ as one input of the ECL circuit 22 through an emitter-followered bipolar transistor T₁₇. The ECL circuit 22 is nearly identical to the ECL circuit 20 shown in FIG. 4 except that a bipolar transistor T₂₁ is inserted in a forward direction between the commonly coupled emitter of the bipolar transistors T₁₈ and T₁₉ and the collector of the transistor T₂₀. The emitter of the transistor T₂₁ is coupled to the emitter of the transistors T₁₅ and T₁₆. Read and write control signals W_(c) and W_(c) are derived from the collectors of the transistors T₁₈ and T₁₉ in the ECL 22. The collectors of the transistors T₁₅ and T₁₆ are commonly coupled to ground potential through IGFETs Q₂₀ and Q₂₁, whose gates are connected to the gates of IGFETs Q₁₈ and Q₁₉ as load elements in the ECL circuit 22, respectively. The gates of IGFETs Q₁₈ and Q₁₉ are also grounded through IGFETs Q₂₂ and Q₂₃. The gates of the transistors Q₂₂ and Q₂₃ are commonly coupled to the collector of the transistors T₁₅ and T₁₆, from which signal W_(E) in reverse phase of the write enable signal W_(E) is led. A table of truth values for this circuit is shown below:

    ______________________________________                                          Function                                                                                ##STR1##                                                                             ##STR2##                                                                              D.sub.IN                                                                            W.sub.E                                                                              W.sub.C                                                                              ##STR3##                                                                             D.sub.OUT                        ______________________________________                                         Non-selection                                                                           H.sub.i                                                                              X      X    -1V   0V    0V    L.sub.o                                                      ˜-2V                                          Writing "H.sub.i "                                                                      L.sub.o                                                                              L.sub.o                                                                               H.sub.i                                                                             0V    0V    -1V   L.sub.o                                                                  ˜-2V                              Writing "L.sub.o "                                                                      L.sub.o                                                                              L.sub.o                                                                               L.sub.o                                                                             0V    -1V   0V    L.sub.o                                                            ˜-2V                                    Read     L.sub.o                                                                              H.sub.i                                                                               X    -1V   0V    0V    L.sub.o /H.sub.i                                             ˜-2V                                          ______________________________________                                          H.sub.i : High Level                                                           L.sub.o : Low Level                                                            X: Any one of H.sub.i or L.sub.o                                         

The signal W_(E) is at a low level during writing. The read and write control signals W_(c) and W_(c) are generated by the circuit operation mentioned below. First, when the chip select signal C_(S) is at a high level, the transistors T₁₈, T₁₉, and T₂₁ become non-conductive regardless of the write enable signal W_(E) or data-in signal D_(IN), and the transistor T₁₆ becomes conductive. For this reason, a current of the regulated power supply consisting of the transistors T₂₀ and Q₂₄ flows from the transistors Q₂₀ and Q₂₁. The drain potentials of IGFETs Q₂₀ and Q₂₁, that is, signal W_(E), become potentials of a low level (-1˜-2 V). IGFETs Q₂₂ and Q₂₃ are enhancement-type transistors, and their threshold voltages are in a range of -0.3 to -0.6 V and conduct when the voltage of -1˜-2 V is applied to their gates, so that both the read and write signals W_(c) and W_(c) are made 0 V. The signals W_(C) and W_(C) become 0 V even when the write enable signal W_(E) is at the high level, as is the case when the chip select signal is at a high level. As the transistor T₂₁ is not conducting, the signal D_(IN) does not affect the levels of the signals W_(C) and W_(C). This state is a read state. As will be stated later, the output will be at a low level if the chip select signal C_(S) is at a high level at the same time, and the semiconductor memory chip will be in a non-selective state. If the signals C_(S) and W_(E) are both at a low level, then the transistor T₂₁ conducts, and the read and write control signals W_(C) and W_(C) become differential signals of 0 V and -1 to -2 V by the level of the data-in signal D_(IN). Needless to say, the gate potentials of IGFETs Q₂₂ and Q₂₃ will accurately be 0 V as the low level of -1 to -2 V is applied to the gate of either one of IGFETs Q₂₀ and Q₂₁. The transistors T₁₃ and T₁₄ and diodes D₅ and D₆ are used merely for level adjustment, and IGFETs Q₁₆, Q₁₇, etc. operate as load elements of the emitter follower circuits as stated above.

The multiplexer 16 shown in FIG. 6 determines one digit line pair among i pairs of digit lines in the memory cell array 11 in accordance with the output Y_(di) of the address driver circuit 13_(y). Only one of Y_(di) (i=1˜i) selected has the low level of -1 to -2 V, and all the others have 0 V. The output signals Y_(di) are given to the gates of the IGFETs Q₂₅, Q₂₆, and Q₂₇. The drains of IGFETs Q₂₈ and Q₂₉ are coupled to the source of IGFET Q₂₇. The source of IGFETs Q₂₈ and Q₂₉ are coupled to the digit lines D_(i) and D_(i), respectively and the gates thereof are supplied with the control signals W_(C) and W_(C). The sources of IGFETs Q₂₅ and Q₂₆ are coupled to the digit lines D_(i) and D_(i), and the drains thereof are grounded. The digit line D_(i) is connected to a low potential point and the ground through IGFETs Q₃₁ and Q₃₃, respectively. The digit line D_(i) connects to a low potential point and the ground through IGFETs Q₃₂ and Q₃₄, respectively.

When the read out state is considered, IGFETs Q₂₈ and Q₂₉ are in a non-conductive state and the potentials of i-l non-selective pairs of digit lines can be shown approximately by the following provided that IGFETs Q₂₅ and Q₂₆ are non-conducting:

    V.sub.Dl =V.sub.EE ×r.sub.34 /(r.sub.32 +r.sub.34),l=i(2)

    V.sub.Dl =V.sub.EE ×{r.sub.33 //(r.sub.QC +r.sub.QT)}/{[r.sub.33 //(r.sub.QC +r.sub.QT)]+r.sub.31 },l≠i              (3)

Wherein conductive resistances of IGFETs Q₂₅ through Q₃₄ are represented by r₂₅ ˜r₃₄, respectively and the impedance of the digit line D_(i) on the conducting side of the memory cell C_(ij) is assumed to be r_(QC) +r_(QT), and the digit line on the non-conducting side of the transistor of the memory cell C_(ij) is assumed to be D_(i). IGFETs Q₂₅ and Q₂₆ conduct, and the potential of the selected digit line pair will be:

    V.sub.Di =V.sub.EE ×(r.sub.26 //r.sub.34)/{(r.sub.26 //r.sub.36)+r.sub.32 }                                    (4)

    V.sub.Di =V.sub.EE {(r.sub.QC +r.sub.QT)//r.sub.25 //r.sub.33 }/{(r.sub.QC +r.sub.QT)//r.sub.25 //r.sub.33)+r.sub.31 }               (5)

When the symmetry of the circuit is considered: r₂₅ =r₂₆, r₃₁ =r₃₂ and r₃₃ =r₃₄. Let us assume further r₂₅ =r₃₁ =r₃₃ =r_(QC) +r_(QT) for the sake of explaining the circuitry operation better. Then, Eqs. (2), (3), (4) and (5) will be V_(Dl) =V_(EE) ×1/3, V_(Di) =V_(EE) ×1/3, and V_(Di) =V_(EE) ×1/4. Therefore, assuming the low potential V_(EE) to be -5.2 V, the potential of the nonselective digit line will be V_(Dl) =-2.6 V and V_(Dl) =-1.7 V, and the potential of the digit lines in the digit line pair to be selected will be V_(Di) =-1.7 V and V_(Di) =1.3 V. Therefore, the contents of the selected memory cell can be read by detecting the differential potential of this digit line pair by the differential amplifier 17. A further explanation of this is omitted as it will be taken up when the differential amplifier 17 is explained in the following section.

Differential signals of 0 V and -1 to -2 V are generated on the write control signal W_(C) and W_(C) to write information in the selected memory cell C_(ij). As the decoder outputs Y_(dl) (l≠i) on the Y side to be supplied to non-selective digit wire pairs are all 0 V, IGFET Q₂₇ becomes non-conductive and the digit line pairs are not affected no matter what voltages may be applied to the gates of the IGFETs Q₂₈ and Q₂₉. While, the digit lines of only one digit line pair selected will have a differential signal according to the D_(IN) input signal in response to the conducting state of IGFETs Q₂₈ and Q₂₉ which receive the signals W_(C) and W_(C) as IGFET Q₂₇ conducts. In this instance, by making the conductive resistance of IGFETs Q₂₇, Q₂₈, and Q₂₉ sufficiently smaller than that of IGFET Q₃₁, etc., the potential of the digit line coupled to conducted one of IGFETs Q₂₈ and Q₂₉ becomes 0 V. Therefore, the potential of this digit line is applied to the gates of IGFET Q₁ and Q₂ of the memory cell through the transfer gates Q₅ and Q₆ (FIG. 1) in the memory cell C_(ij) so that the content of this memory cell can be reversed.

The differential amplifier 17 shown in FIG. 8 detects and amplifies the differential potential of the digit line pair. The differential amplifier 25 includes bipolar transistors T₂₄, T₂₅, T₂₆, and T₂₇ which are current-amplification connected. Digit lines D_(i) and D_(i) are coupled to the bases of the transistors T₂₄ and T₂₆, which are two inputs for the differential amplifier 25 respectively. The collectors of the transistors T₂₅ and T₂₇, from which outputs of the differential amplifier 25 are derived, are coupled to sense lines SA and SA, respectively. The emitters of the transistors T₂₅ and T₂₇ are coupled to the low potential V_(EE) through a line SA₁ and a regulated power supply circuit made of transistors T₂₈ and Q₃₅. The bases of the transistors T₂₅ and T₂₇ are coupled to the low potential V_(EE) through IGFETs Q₃₉ and Q₄₁ acting as resistance elements, respectively. The sense lines SA and SA are coupled to the emitters of the transistors T₃₃ and T₃₄ in the detection circuit 26, respectively, and to the low potential V_(EE) through regulated power supply circuits made of the transistors (T₂₉, Q₃₆), and (T₃₁, Q₃₇) respectively. The collectors of the transistors T₃₃ and T₃₄ are coupled to the ground through IGFETs Q₄₄ and coupled to the low potential V_(EE) through a regulated current source made of the transistors T₃₂ and Q₃₈. The transistors T₃₃ and T₃₄ constitute a base-grounded type impedance conversion circuit which reduces effects of the capacities of the sense lines SA and SA.

The potentials generated on one digit line pair becomes -2.6 V (1/2 V_(EE)) and -1.73 V (1/3 V_(EE)) on a non-selective digit line pair and -1.73 (1/3 V_(EE)) and -1.3 V (1/4 V_(EE)) on a selected digit line pair, as stated in the explanation for the multiplexer 16. For this reason, the commonly coupled emitters of all of the i pieces of differential amplifiers 16 are commonly coupled to a regulated power supply made of the transistors T₂₈ and Q₃₅. As a result, the transistor that has the highest input level of the differential amplifier 17 conducts, conducting only the transistor applied with -1.3 V, which is higher one of -1.73 V and -1.3 V of the potentials of the digit line pair selected.

The potential of the digit line pair detected by the differential amplifier 17 is amplified by the output amplifier circuit 15 in which the output lines S and S are supplied to the emitter-followed bipolar transistors T₃₆ and T₃₇ as shown in FIG. 9. Outputs therefrom are supplied to the bases of the input bipolar transistors T₃₈ and T₃₉ in the ECL circuit 27 which is similar to the ECL circuit 22 in FIG. 7. The collector of the transistor T₃₉ is supplied to the base of the bipolar transistor T₄₁, whose collector is grounded and whose emitter supplies output to the terminal 28. The collector of the transistor T₃₉ in the ECL circuit 27 is coupled to the collector of the transistor T₄₃ as regulated power supply through the transistor T₄₂. The chip select signal C_(S) and the signal W_(E) from the read and write control circuit 14 are supplied to the bases of the transistors T₄₄ and T₄₅, respectively. The emitters of these transistors T₄₄ and T₄₅ are commonly coupled to the base of the transistor T₄₂ and to the low potential V_(EE) through IGFET Q₄₇. Consequently, when the line S from the differential amplifier 17 is at a high level and the output terminal 28 is at a high level. While the terminal 28 is at a low level when the line S is at a high level. When logical OR output of the signals C_(S) and W_(E) is at a high level, the transistor T₄₂ conducts, and the output terminal 28 will be at a low level regardless of the read signals from the memory cells.

Next, comparisons of above-described embodiment with a MOS RAM employing only IGFETs and a bipolar RAM employing only bipolar transistors will be shown in case of a memory capacity of one kilobits as an example.

Table 1 shows delay times for each function block shown in FIG. 3 and for total for each case regarding delay time.

                  TABLE 1                                                          ______________________________________                                                   Block                                                                          (Unit: ns)                                                                     12.sub.x                                                                            13.sub.x                                                                              11      17   15   Total                                  ______________________________________                                         Present Invention                                                                          2      3      7     2    2    16                                   (ECL interface)                                                                MOS RAM     3      5      10    5    7    30                                   (TTL interface)                                                                Bipolar RAM 2      3      5     2    2    14                                   (ECL)                                                                          ______________________________________                                    

Table 1 shows that a read time of 16 ns, which is substantially equivalent to 14 ns for the bipolar RAM, has been realized by the invention. This means that a high speed equivalent to that of a bipolar RAM can be realized by the invention.

In a similar context, integration will be studied next.

Table 2 shows areas per function block shown in FIG. 3 and total chip areas for the present invention, MOS RAM and bipolar RAM.

                  TABLE 2                                                          ______________________________________                                         Block                                                                          (Unit: mm.sup.2)                                                               11       12.sub.x                                                                             13.sub.x                                                                             12.sub.y                                                                           13.sub.y                                                                           16  17  14  19  Others                                                                               Total                       ______________________________________                                         Present                                                                               2.4   0.3   0.7 0.3 0.6 0.3 0.2 0.1 0.3 1.4   6.9                       Invention                                                                      MOS    2.4   0.2   0.6 0.2 0.1 0.1 0.1 --  1.0 1.2   6.0                       RAM                                                                            Bipolar                                                                               5.5   0.3   0.7 0.3 0.6 0.3 0.3 0.1 0.3 2.0   10.6                      RAM                                                                            ______________________________________                                    

The column for "Others" in Table 2 shows regions for bonding pads, etc.

Table 2 shows that the present invention can be realized in a small area nearly the same as that for MOS RAM and that it has a high integration degree.

Above, the effects of the present invention have been explained with an example for a one-kilobit chip. The effects of the present invention, that is, a simultaneous realization of high speed and high integration, will be clearer the larger the capacities of RAMs such as 16 and 64 kilobit RAMs. 

I claim:
 1. A memory device comprising:a plurality of memory cells arrayed in rows and columns, each of said memory cells having a pair of cross-coupled insulated-gate field effect transistors, at least one address inverter circuit for generating true and complement signals of an address signal, said address inverter circuit including first and second bipolar transistors having commonly connected emitters, a constant current source coupled to said commonly connected emitters, a first field effect transistor connected between a predetermined voltage and the collector of said first bipolar transistor, a second field effect transistor connected between said predetermined voltage and the collector of said second transistor, means for connecting the gate of said first field effect transistor to the collector of said second bipolar transistor, means for connecting the gate of said second field effect transistor to the collector of said first bipolar transistor, means for supplying the base of said first bipolar transistor with said address signal, and means for supplying the base of said second transistor with a reference voltage, said true and complement signals being derived from the collectors of said second and first bipolar transistors respectively, row drive means responsive to the output of said address inverter for selectively energizing one of said rows, said row drive means including an emitter coupled logic circuit, and a read circuit for sensing data stored in selected ones of said memory cells, and read circuit including third and fourth bipolar transistors having commonly connected emitters, a constant current source coupled to said commonly connected emitters of said third and fourth bipolar transistors, and means for supplying the bases of said third and fourth bipolar transistors with a differential signal derived from selected memory cell.
 2. The memory device according to claim 1, in which said emitter coupled logic circuit included in said row drive means includes a fifth and a sixth bipolar transistors having commonly connected emitters, a constant current source coupled to said commonly connected emitters of said fifth and sixth transistors, a third field effect transistor connected between said predetermined voltage and the collector of said fifth bipolar transistor, a fourth field effect transistor connected between said predetermined voltage and the collector of said sixth bipolar transistor, means for connecting the gate of said third field effe transistor to the collector of said sixth bipolar transistors, means for connecting the gate of said fourth field effect transistor to the collector of said fifth bipolar transistor, means for supplying the base of said sixth bipolar transistor with said reference voltage, and means for supplying the base of said fifth bipolar transistor with a decoded address signal.
 3. The memory device according to claim 1, in which said first and second field effect transistors are of the depletion type.
 4. A memory device comprising:a plurality of memory cells including insulated-gate field effect transistors, a selection circuit responsive to address signal for selecting said memory cells, said selection circuit including first and second bipolar transistors having commonly connected emitters, a current source connected to said commonly connected emitters, a first load element including a first field effect transistor connected to the collector of said first bipolar transistor, and a second load element including a second field effect transistor connected to the collector of said second bipolar transistor, said first and second bipolar transistors being driven in a differential manner by said address signal, and a sense circuit for detecting stored data of selected memory cells, said sense circuit including third and fourth bipolar transistors having commonly connected emitters, a current source coupled to said commonly connected emitters, a third load element including a third field effect transistor coupled to the collector of said third bipolar transistor, a fourth load element including a fourth field effect transistor coupled to the collector of said fourth bipolar transistor and means for supplying the bases of said third and fourth bipolar transistors with differential signal derived from selected memory cells thereby to operate said third and fourth bipolar transistors as an emitter-coupled logic circuit.
 5. The device according to claim 4, in which said first to fourth field effect transistors are of the depletion type.
 6. The device according to claim 4, further comprising means for connecting the gate of said third field effect transistor to the collector of said fourth bipolar transistor, and means for connecting the gate of said fourth field effect transistor to the collector of said third bipolar transistor.
 7. A semiconductor memory comprising a plurality of memory cells, each of said memory cells including binary storage means and at least one transfer gate composed of an insulated gate field effect transistor, and a peripheral circuit for operatively driving the memory cell from which the stored content is read out, said peripheral circuit including at least one emitter coupled logic circuit, said emitter coupled logic circuit including first and second bipolar transistors having commonly connected emitters, a constant current source coupled to said commonly connected emitters, a first load element of a first field effect transistor coupled to the collector of said first bipolar transistor and a second load element of a second field effect transistor coupled to the collector of said second bipolar transistor.
 8. A semiconductor circuit comprising first and second bipolar transistors, the emitters of said first and second transistors being commonly connected, a first voltage terminal, a second voltage terminal, a first field effect transistor connected between said first voltage terminal and the collector of said first bipolar transistor, a second field effect transistor connected between said first voltage terminal and the collector of said second bipolar transistor, a constant current source connected between said second voltage terminal and said emitters of said first and second bipolar transistors, and means for supplying the bases of said first and second bipolar transistors with a pair of signals having different potentials, a pair of output signals being derived from the collectors of said first and second bipolar transistors.
 9. The circuit according to claim 8, in which the gate of said first field effect transistor is connected to the collector of said second bipolar transistor and the gate of said second field effect transistor is connected to the collector of said first bipolar transistor.
 10. The circuit according to claim 9, in which said first and second field effect transistors are of the depletion type. 